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Errata #874(bsa): Add SMMU_03 atomicity coverage #582

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Merged
chetan-rathore merged 1 commit into from
Oct 1, 2026
Merged

Errata #874(bsa): Add SMMU_03 atomicity coverage #582

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1 change: 1 addition & 0 deletions apps/uefi/Bsa.inf
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Expand Up @@ -221,6 +221,7 @@
../../test_pool/smmu/i024.c
../../test_pool/smmu/i025.c
../../test_pool/smmu/i026.c
../../test_pool/smmu/i033.c
../../test_pool/memory_map/m005.c
../../test_pool/pcie/p004.c
../../test_pool/pcie/p005.c
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1 change: 1 addition & 0 deletions apps/uefi/Sbsa.inf
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Expand Up @@ -223,6 +223,7 @@
../../test_pool/smmu/i024.c
../../test_pool/smmu/i025.c
../../test_pool/smmu/i026.c
../../test_pool/smmu/i033.c
../../test_pool/memory_map/m005.c
../../test_pool/pcie/p004.c
../../test_pool/pcie/p005.c
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1 change: 1 addition & 0 deletions apps/uefi/SbsaNist.inf
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Expand Up @@ -100,6 +100,7 @@
../../test_pool/smmu/i024.c
../../test_pool/smmu/i025.c
../../test_pool/smmu/i026.c
../../test_pool/smmu/i033.c
../../test_pool/memory_map/m001.c
../../test_pool/memory_map/m005.c
../../test_pool/pcie/p001.c
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1 change: 1 addition & 0 deletions apps/uefi/Vbsa.inf
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Expand Up @@ -224,6 +224,7 @@
../../test_pool/smmu/i024.c
../../test_pool/smmu/i025.c
../../test_pool/smmu/i026.c
../../test_pool/smmu/i033.c
../../test_pool/memory_map/m005.c
../../test_pool/pcie/p004.c
../../test_pool/pcie/p005.c
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1 change: 1 addition & 0 deletions apps/uefi/pc_bsa.inf
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Expand Up @@ -222,6 +222,7 @@
../../test_pool/smmu/i024.c
../../test_pool/smmu/i025.c
../../test_pool/smmu/i026.c
../../test_pool/smmu/i033.c
../../test_pool/memory_map/m005.c
../../test_pool/pcie/p004.c
../../test_pool/pcie/p005.c
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1 change: 1 addition & 0 deletions apps/uefi/xbsa_acpi.inf
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Expand Up @@ -218,6 +218,7 @@
../../test_pool/smmu/i024.c
../../test_pool/smmu/i025.c
../../test_pool/smmu/i026.c
../../test_pool/smmu/i033.c
../../test_pool/memory_map/m005.c
../../test_pool/pcie/p004.c
../../test_pool/pcie/p005.c
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48 changes: 44 additions & 4 deletions docs/bsa/arm_bsa_testcase_checklist.md
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Expand Up @@ -603,8 +603,8 @@ The checklist provides information about:
<td></td>
</tr>
<tr>
<td>L1</td>
<td>B_SMMU_08</td>
<td rowspan="4">L1</td>
<td rowspan="4">B_SMMU_08</td>
<td>B_SMMU_08</td>
<td>304</td>
<td>Check SMMU S-EL2 &amp; stage1 support</td>
Expand All @@ -614,6 +614,36 @@ The checklist provides information about:
<td></td>
<td></td>
</tr>
<tr>
<td>SMMU_01</td>
<td>307</td>
<td>SMMUv3 Integration compliance</td>
<td>Yes</td>
<td>Yes</td>
<td>No</td>
<td></td>
<td></td>
</tr>
<tr>
<td>SMMU_02</td>
<td>Not Covered</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>ACS detects advertised stall support through IDR0.STALL_MODEL only; rule compliance requires integration/DV evidence.</td>
<td></td>
</tr>
<tr>
<td>SMMU_03</td>
<td>333</td>
<td>Check SMMU 128-bit atomicity support</td>
<td>Yes</td>
<td>Yes</td>
<td>No</td>
<td></td>
<td></td>
</tr>
<tr>
<td>L1</td>
<td>B_SMMU_12</td>
Expand Down Expand Up @@ -675,8 +705,8 @@ The checklist provides information about:
<td></td>
</tr>
<tr>
<td rowspan="2">L1</td>
<td rowspan="2">B_SMMU_21</td>
<td rowspan="3">L1</td>
<td rowspan="3">B_SMMU_21</td>
<td>SMMU_01</td>
<td>307</td>
<td>SMMUv3 Integration compliance</td>
Expand All @@ -696,6 +726,16 @@ The checklist provides information about:
<td>ACS detects advertised stall support through IDR0.STALL_MODEL only; rule compliance requires integration/DV evidence.</td>
<td></td>
</tr>
<tr>
<td>SMMU_03</td>
<td>333</td>
<td>Check SMMU 128-bit atomicity support</td>
<td>Yes</td>
<td>Yes</td>
<td>No</td>
<td></td>
<td></td>
</tr>
<tr>
<td>L1</td>
<td>B_TIME_01</td>
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12 changes: 10 additions & 2 deletions docs/pc_bsa/arm_pc-bsa_testcase_checklist.md
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Expand Up @@ -328,8 +328,8 @@ The checklist provides information about:
<tr>
<td>307</td>
<td>SMMU_01: SMMUv3 Integration compliance</td>
<td rowspan="2">1</td>
<td rowspan="2">P_L1SM_04</td>
<td rowspan="3">1</td>
<td rowspan="3">P_L1SM_04</td>
<td>Yes</td>
<td>Yes</td>
<td>Yes</td>
Expand All @@ -343,6 +343,14 @@ The checklist provides information about:
<td></td>
<td></td>
</tr>
<tr>
<td>333</td>
<td>SMMU_03: Check SMMU 128-bit atomicity support</td>
<td>Yes</td>
<td>Yes</td>
<td>Yes</td>
<td>No</td>
</tr>
<tr>
<td>322</td>
<td>Check if all DMA reqs behind SMMU</td>
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14 changes: 12 additions & 2 deletions docs/sbsa/arm_sbsa_testcase_checklist.md
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Expand Up @@ -314,8 +314,8 @@ The checklist provides information about:
<td></td>
</tr>
<tr>
<td rowspan="2">L4</td>
<td rowspan="2">S_L4SM_03</td>
<td rowspan="3">L4</td>
<td rowspan="3">S_L4SM_03</td>
<td>SMMU_01</td>
<td>307</td>
<td>SMMUv3 Integration compliance</td>
Expand All @@ -335,6 +335,16 @@ The checklist provides information about:
<td>ACS detects advertised stall support through IDR0.STALL_MODEL only; rule compliance requires integration/DV evidence.</td>
<td></td>
</tr>
<tr>
<td>SMMU_03</td>
<td>333</td>
<td>Check SMMU 128-bit atomicity support</td>
<td>Yes</td>
<td>Yes</td>
<td>No</td>
<td></td>
<td></td>
</tr>
<tr>
<td>L4</td>
<td>S_L4PCI_1</td>
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2 changes: 1 addition & 1 deletion docs/vbsa/arm_vbsa_architecture_compliance_test_scenario.md
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Expand Up @@ -150,7 +150,7 @@ Purpose: capture ACS scenario outlines for each VBSA rule. Each section:
---

### V_L1SM_02 — Check SMMU stage 1 support for VE
**Summary**: Invoke the test that verified B_SMMU_08, ensuring that S-EL2 check is disabled.
**Summary**: Verify SMMU stage 1 support with the S-EL2 check disabled, then run the SMMU_01, SMMU_02, and SMMU_03 integration rules required by B_SMMU_08.

#### Related BSA Rule
- #### B_SMMU_08 — see section 2.5 in [BSA ACS Scenario Document](../bsa/arm_bsa_architecture_compliance_test_scenario.pdf#page16&search=B_SMMU_08)
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32 changes: 28 additions & 4 deletions docs/vbsa/arm_vbsa_testcase_checklist.md
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Expand Up @@ -314,14 +314,38 @@ The checklist provides information about:
<td></td>
</tr>
<tr>
<td>L1</td>
<td><a href="arm_vbsa_architecture_compliance_test_scenario.md#v_l1sm_02--check-smmu-stage-1-support-for-ve">V_L1SM_02</td>
<td></td>
<td rowspan="4">L1</td>
<td rowspan="4"><a href="arm_vbsa_architecture_compliance_test_scenario.md#v_l1sm_02--check-smmu-stage-1-support-for-ve">V_L1SM_02</td>
<td>V_L1SM_02</td>
<td>331</td>
<td>Check SMMU stage 1 support for VE</td>
<td>✅</td>
<td>❌</td>
<td>Related rules from other specifications: B_SMMU_08 (BSA)</td>
<td>Related rule from BSA: B_SMMU_08</td>
</tr>
<tr>
<td>SMMU_01</td>
<td>307</td>
<td>SMMUv3 Integration compliance</td>
<td>✅</td>
<td>❌</td>
<td></td>
</tr>
<tr>
<td>SMMU_02</td>
<td>Not Covered</td>
<td></td>
<td>❌</td>
<td>❌</td>
<td>ACS detects advertised stall support through IDR0.STALL_MODEL only; rule compliance requires integration/DV evidence.</td>
</tr>
<tr>
<td>SMMU_03</td>
<td>333</td>
<td>Check SMMU 128-bit atomicity support</td>
<td>✅</td>
<td>❌</td>
<td></td>
</tr>
<tr>
<td>L1</td>
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104 changes: 104 additions & 0 deletions test_pool/smmu/i033.c
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@@ -0,0 +1,104 @@
/** @file
* Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved.
* SPDX-License-Identifier : Apache-2.0

* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
**/

#include "acs_val.h"
#include "acs_pe.h"
#include "val_interface.h"
#include "acs_smmu.h"

#define TEST_NUM (ACS_SMMU_TEST_NUM_BASE + 33)
#define TEST_RULE "SMMU_03"
#define TEST_DESC "Check SMMU 128-bit atomicity support "

#define SMMU_IDR5_D128_BIT 8

static
void
payload()
{
uint32_t index;
uint32_t num_smmu;
uint32_t smmu_index;
uint32_t lse2_feat;
uint32_t d128;
uint32_t relevant_smmu = 0;

index = val_pe_get_index_mpid(val_pe_get_mpid());

/* ID_AA64MMFR2_EL1.AT != 0 indicates that the PE implements FEAT_LSE2. */
lse2_feat = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 32, 35);

if (lse2_feat == 0) {
val_print(DEBUG, "\n SMMU_03 not applicable: FEAT_LSE2 not supported");
val_set_status(index, RESULT_SKIP(1));
return;
}

num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
if (num_smmu == 0) {
val_print(DEBUG, "\n No SMMU Controllers are discovered");
val_set_status(index, RESULT_SKIP(2));
return;
}

for (smmu_index = 0; smmu_index < num_smmu; smmu_index++) {
/* SMMU_IDR5.D128 is defined for SMMUv3 controllers. */
if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, smmu_index) < 3) {
val_print(DEBUG, "\n SMMU %x is not an SMMUv3 controller", smmu_index);
continue;
}

relevant_smmu++;
/* IDR5.D128 indicates support for the required 128-bit atomicity. */
d128 = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR5, smmu_index),
SMMU_IDR5_D128_BIT, SMMU_IDR5_D128_BIT);
val_print(DEBUG, "\n SMMU %x IDR5.D128 = 0x%x", smmu_index, d128);

if (d128 == 0) {
val_print(ERROR, "\n SMMU does not support 128-bit single-copy atomicity");
val_set_status(index, RESULT_FAIL(1));
return;
}
}

if (relevant_smmu == 0) {
val_print(DEBUG, "\n SMMU_03 not applicable: No SMMUv3 controllers");
val_set_status(index, RESULT_SKIP(3));
return;
}

val_set_status(index, RESULT_PASS);
}

uint32_t
i033_entry(uint32_t num_pe)
{
uint32_t status = ACS_STATUS_FAIL;

num_pe = 1; // This test is run on a single processor

val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__);
status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);

if (status != ACS_STATUS_SKIP)
val_run_test_payload(TEST_NUM, num_pe, payload, 0);

status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE);
val_report_status(0, ACS_END(TEST_NUM), TEST_RULE);

return status;
}
1 change: 1 addition & 0 deletions tools/cmake/infra/bsa_test.txt
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Expand Up @@ -85,6 +85,7 @@ i018.c
i019.c
i025.c
i026.c
i033.c
p001.c
p002.c
p003.c
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1 change: 1 addition & 0 deletions tools/cmake/infra/pc_bsa_test.txt
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Expand Up @@ -65,6 +65,7 @@ i008.c
i022.c
i025.c
i026.c
i033.c
m001.c
m002.c
m003.c
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1 change: 1 addition & 0 deletions tools/cmake/infra/sbsa_test.txt
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Expand Up @@ -62,6 +62,7 @@ i023.c
i024.c
i025.c
i026.c
i033.c
m005.c
p001.c
p002.c
Expand Down
1 change: 1 addition & 0 deletions val/include/acs_smmu.h
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Expand Up @@ -89,5 +89,6 @@ uint32_t i029_entry(uint32_t num_pe);
uint32_t i030_entry(uint32_t num_pe);
uint32_t i031_entry(uint32_t num_pe);
uint32_t i032_entry(uint32_t num_pe);
uint32_t i033_entry(uint32_t num_pe);

#endif
2 changes: 2 additions & 0 deletions val/include/rule_based_execution_enum.h
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Expand Up @@ -250,6 +250,7 @@ typedef enum {
B_SMMU_25,
SMMU_01,
SMMU_02,
SMMU_03,
S_L4SM_01,
S_L3SM_01,
S_L4SM_02,
Expand Down Expand Up @@ -765,6 +766,7 @@ typedef enum {
I028_ENTRY,
I031_ENTRY,
I032_ENTRY,
I033_ENTRY,
T001_ENTRY,
T002_ENTRY,
T003_ENTRY,
Expand Down
1 change: 1 addition & 0 deletions val/src/pc_bsa_execute_test.c
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Expand Up @@ -181,6 +181,7 @@ val_pcbsa_smmu_execute_tests(uint32_t level, uint32_t num_pe)

status |= i007_entry(num_pe);
status |= i032_entry(num_pe);
status |= i033_entry(num_pe);
status |= i022_entry(num_pe);
}

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1 change: 1 addition & 0 deletions val/src/rule_enum_string_map.c
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Expand Up @@ -222,6 +222,7 @@ char *rule_id_string[RULE_ID_SENTINEL] = {
[B_SMMU_25] = "B_SMMU_25",
[SMMU_01] = "SMMU_01",
[SMMU_02] = "SMMU_02",
[SMMU_03] = "SMMU_03",
[S_L3SM_01] = "S_L3SM_01",
[S_L4SM_01] = "S_L4SM_01",
[S_L4SM_02] = "S_L4SM_02",
Expand Down
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