Instantaneous Spectrum Analser Built for the Tang Nano 20K FPGA development board.
Work in Progress
Flash to Tang Nano 20K
# flash volatile sram memory
make flash-sram
# flash nonvolatile memory
make flashrun isolated builds
~/oss-cad-suite/bin/yosys -p "read_verilog -sv src/[FILE_NAME].sv"Simulation
# Run default top integration test
make sim
# Run a specific testbench
make sim TB=pll_pixel_tb
make sim TB=sim/top_tb.v
# View simulation waveforms in GTKWave / Surfer
make waves
make waves TB=pll_pixel_tbClean Build Files
make cleanCheck toolchain status
make check-toolsInstall OSS CAD Suite
make setup-toolchainSD = Serial Data
MS = Word Select (WS / LRCK) - determines left or right channel
CCK = Serial Clock (SCK / BCLK) - synchronises the bits
L/R = Channel Select (Tie to GND for left, VDD for right)
Refer to docs/ folder
- Pixel Clock 74.25 MHz (for 1280×720 @ 60 Hz HDMI video)
- Serial Clock 371.25 MHz (5× DDR for 10:1 TMDS bit serialization)
Clocking and Reset:
src/pll_pixel.svsrc/reset_sync.svsrc/cdc_sync.sv
Video Pipeline:
src/video_sync.svsrc/tmds_encoder.svsrc/hdmi_tx.sv
Top Level:
src/top.sv
1280 x 720 = 201 600 Xbits: 2^11 = 2047 Ybits: Xbits for consitency